1. Field of the Invention
The present invention relates to a memory controller, a cache device, a memory control system, a memory control method, and a recording medium, particularly to a technique for controlling a storage device in which data I/O is made fast.
2. Description of the Related Art
In recent years, as the clock speeds of CPUs in computer systems become higher or the processing speeds of various other electronic circuits become higher, high-speed interfaces are required. For this purpose, by exploiting the fact that addresses of a storage device successively output from a CPU are mostly near to each other, DRAMs (Dynamic Random Access Memories) after a high-speed DRAM use a function of keeping an area, which has been activated in a memory cell array, active for a while to achieve the faster subsequent access to the area.
FIG. 1 shows a schematic arrangement of a DRAM. Referring to FIG. 1, a memory cell array 35 comprises a plurality of word lines, a plurality of bit lines perpendicular to the word lines, and a plurality of memory cells located at the intersections of the word and bit lines. Upper bits of an address externally input to an address buffer 31 indicate a row address, and lower bits thereof indicate a column address. The row address is held in a row address buffer 32, and the column address is held in a column address buffer 33.
The row address held in the row address buffer 32 is decoded by a row decoder 34 to select one word line in the memory cell array 35. In a readout operation, data in the respective memory cells connected to the selected word line are read out onto the corresponding bit lines as small voltages, which are amplified by a sense amplifier 36.
The column address held in the column address buffer 33 is decoded by a column decoder 37 to open the column gate for one bit line corresponding to the decoded column address. Data on the thus selected bit line is output onto a common line 40 through the opened column gate. In a readout operation, the thus obtained data DQ is externally output through a data I/O buffer 38.
In a writing operation, data DQ externally input through the data I/O buffer 38 is supplied to a bit line in the memory cell array 35 through the common line 40 and the corresponding column gate selected according to a given column address. The data is written in a memory cell on the intersection of the bit line and a word line selected according to a given row address.
The above-mentioned elements 31 to 38 are under control of a control circuit 39. The control circuit 39 is externally supplied with a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE. Note that an inverted signal expressed by a signal name with an overline in FIG. 1 (and FIGS. 7 to 10) will be expressed by attaching symbol xe2x80x9c/xe2x80x9d to the signal name in the specification.
In this type of DRAM, successive accesses for readout and writing (read/write) are mostly done to addresses near to each other. After completion of an access to a row address, the same row address is more likely to be accessed next. For this reason, when there arises no necessity to make an access to a different row address, a word line selected according to a row address is kept active so that the subsequent accesses can be made by selecting a column address only. A faster access is thereby attained.
In order to use such a function more effectively, a recent memory controller controls a block of a predetermined size (one word line) to be kept active even after data in the block was accessed according to a given address, so as to be able to respond faster when the same block is successively accessed. The unit size for such a block is called xe2x80x9cpagexe2x80x9d, and there is a case that a DRAM utilizing this function is called xe2x80x9cfast page DRAMxe2x80x9d.
On the other hand, it is a common practice for recent computer systems to insert a cache memory, which is composed of memory elements faster than those of a main memory, between a CPU and the main memory for the reason that data once accessed is more likely to be accessed again in the near future. More specifically, once accessed data in the main memory is registered in the cache memory, and, when the same data is accessed next, it is read out from not the main memory but the cache memory. The access speed to the main memory is thereby apparently increased.
In this computer system with the cache memory, when an access request to data in the main memory is issued, the cache memory is first referred to. If the requested data is present in the cache memory (cache hit), the data is immediately transferred to a CPU. If the requested data is not present in the cache memory (cache miss), a block of an appropriate size including the requested data is read out from the main memory, and stored in the cache memory. At this time, if no empty block is available in the cache memory, a block that is least likely to be used again is selected and replaced by the new data.
Cache memories are roughly classified into store-through type and store-back type. In the store-through type, when the cache contents are rewritten, the main memory contents are always rewritten accordingly, so that the latest data are surely stored also in the main memory. Contrastingly in the store-back type, only the cache contents are rewritten, and, when a block is to be re-assigned due to a cache miss, the latest contents of the cache memory is written back to the main memory. In case of the store-back type, there is therefore a case that the contents of the cache memory differ from those of the corresponding part of the main memory.
In the store-back type, the area in the cache memory where only cache contents have been rewritten is called xe2x80x9cdirty entryxe2x80x9d. When blocks are re-assigned, as to a block including no dirty entry, the corresponding block can be simply loaded from the main memory. As to a block including a dirty entry, however, its contents must be written out to the corresponding block in the main memory, and then another block in the main memory is assigned to the block in the cache memory. Such an operation is called xe2x80x9creplacement of dirty entryxe2x80x9d.
In recent years, as CPUs become faster and cache capacities become larger, the store-through type that must frequently access a main memory is being replaced by the store-back type that must less frequently access the main memory. This is because the access speed to a memory is often considered an important factor of the performance of a data processing system.
FIG. 2 shows a schematic arrangement of a cache memory. As shown in FIG. 2, the cache memory generally comprises a cache (data area) 41 for storing some data stored in a main memory, and a tag memory (tag area) 42 for storing a part of the address (tag) on the main memory corresponding to each of the data stored (as entries) in the cache 41.
Since the cache 41 has a smaller capacity than the main memory, the addresses corresponding to respective entries in the cache 41 are registered in the tag memory 42. The address of data requested by an access request from a CPU is compared with each of the registered addresses in the tag memory 42. A cache hit or miss is determined by judging whether or not the address of the requested data coincides with one of registered addresses in the tag memory 42, i.e., whether the requested data is present in the cache 41 or not.
In this case, however, huge-size hardware is required if the address of the requested data is straightly compared with all of the entries in the cache 41, i.e., all of the tags in the tag memory 42. For this reason, the following scheme (set associative memory scheme) is used in general. Entries having lower bits equal to those (INDEX) of the address attendant upon the access request are selected from among all entries in the cache 41, and then the address is compared with the tags of only the selected entries in a comparator 43. Using the lower bits of the address attendant upon the access request is because of intensive localization of successive access requests from the CPU. Successive accesses are apt to concentrate in a narrow range of addresses.
The same applies to memory control of such a fast page DRAM as described above. More specifically, a row address of the DRAM is assigned to an upper address portion, and a column address is assigned to a lower address portion, so that successive access requests have an identical row address (page hit) with high probability. When a page hit occurs, the subsequent access is controlled only with output a column address while the hit page is kept active (page access scheme). The access speed increases because no row address need be output.
When a recently prevalent store-back cache memory is connected to a memory controller for a conventional fast page DRAM, however, the following problem arises. When a main memory is accessed for performing a replacement of dirty entry in the store-back cache memory, successive access requests having an identical lower address but different upper addresses are made with high probability, and, in most cases, page misses occur in the main memory.
When either of the successive access requests result in a page hit, faster accesses can be assured. But, when a page miss arises in successive access requests due to a difference in row address, overhead arises in the subsequent access, in which the page having been selected according to the preceding access is precharged to return from the active state to the non-activated state (called idle state) before the aimed page is activated.
In a memory controller for a synchronous DRAM (SDRAM: Synchronous Dynamic Random Access Memory), the overhead ratio is especially high because of a high-speed interface. When a benchmark test was performed in which the run time of a standard program with frequent accesses to different memory areas was measured using such an SDRAM memory controller and a store-back cache memory, nearly 20% overhead was observed. When overhead arises, the access speed lowers accordingly.
FIG. 3 is a flow chart showing the flow of page control in a conventional memory controller. Referring to FIG. 3, after a DRAM is reset (step S1), it is in the idle state in which none of word lines is selected (step S2). If an access request is given by a CPU (step S3), one word line (page) is selected according to a row address attendant upon the access request, and activated (step S4). One bit line is then selected according to a column address attendant upon the access request, and a read/write operation is performed. After that, the selected page is kept active.
If no access request is given by the CPU in the step S3, it is checked whether the DRAM is to be refreshed or not (step S8). If NO in the step S8, the flow returns to the step S2 to wait for an access request. Otherwise, the DRAM is refreshed (step S11).
Also in case that no access request is given by the CPU while a page is active (step S5), it is checked whether the DRAM is to be refreshed or not (step S9). If NO in the step S9, the flow returns to the step S4 to wait for an access request. If it is judged in the step S9 that the DRAM is to be refreshed, the currently selected page is precharged (step S10), and then the DRAM is refreshed (step S11).
If an access request is given by the CPU in the step S5, a page hit or miss is judged by checking whether or not the row address attendant upon the access request is the same as the row address given the last time (step S6). In case of page hit, the flow returns to the step S4 to keep the page corresponding to the row address active, and a read/write operation is immediately performed according to the column address attendant upon the access request.
In case of page miss in the step S6, the currently selected page is precharged (step S7) to return from the active state to the idle state (step S2). After that, the flow advances to the step S4 via the step S3 to activate another page. That is, in case of page miss, overhead arises that the currently selected page must be returned from the active state to the idle state before another page is activated.
It is an object of the present invention to attain a more faster access speed to a memory having a fast page function that the page activated according to an access is kept in the active state after that so as to make the subsequent access to the same page faster, by obviating the necessity of resetting the page from the activated state to the idle state when a page miss occurs.
A memory controller according to the present invention is for controlling access to a main memory. The controller has a mode for keeping the accessed page in the main memory active even after the access is completed, and comprises state control circuit for controlling to precharge the accessed page in the main memory to return to the idle state upon completion of preceding access on condition that access to the main memory is attendant upon a replacement of dirty entry in a cache device.
A store-back cache device according to the present invention comprises detection/notification circuit for detecting occurrence of replacement of dirty entry, and sending a signal to a controller of a main memory. The signal indicates whether or not the current access to the main memory is attendant upon the replacement of dirty entry.
A memory control system according to the present invention substantially comprises the above memory controller and the above cache device.
When an access to the main memory is done for a replacement of dirty entry in the cache device, the succeeding access to the main memory highly probably results in a page miss. According to the present invention, however, since the active page in the main memory is precharged to return to the idle state upon completion of preceding access before the succeeding access attendant upon the replacement of dirty entry is completed, the succeeding access can be done only by activating the aimed page in the idle state. It is thereby obviated to return the activated page due to the preceding access to the idle state after a page miss occurs in the succeeding access.
A memory controller according to another aspect of the present invention is for controlling access to a plurality of main memories. The controller has a mode for keeping the accessed page in one of the main memories active even after the corresponding access is completed, and comprises state control circuit for controlling to precharge the accessed page in one of the main memories to return to the idle state upon completion of preceding access on condition that successive accesses attendant upon a replacement of dirty entry in a cache device are made to the same one of said main memories.
A store-back cache device according to another aspect of the present invention comprises detection/notification circuit for detecting occurrence of replacement of dirty entry in a cache and a condition that successive accesses attendant upon the replacement are made to the same one of a plurality of main memories, to send a signal to a controller of the main memories. The signal indicates whether or not the current access to the one of the main memories is attendant upon the replacement of dirty entry.
A memory control system according to another aspect of the present invention substantially comprises the above second memory controller and the above second cache device.
According to the second aspect of the present invention, even when a dirty entry is replaced, if successive accesses attendant upon the replacement of dirty entry are made to different main memories, respectively, control is made not to precharge the active page in the earlier accessed main memory.
Even in accessing for a replacement of dirty entry in the cache device, if different main memories are to be successively accessed, a page miss hardly occurs at that time. So, according to the present invention, when different main memories are successively accessed, precharging is not performed. Unnecessarily precharging can be avoided thereby.
According to still another aspect of the present invention, when a signal indicating whether the present access is attendant upon a replacement of dirty entry or not is sent from the cache device to the memory controller, the signal is included in a signal for indicating a type of access to the main memory.
According to this aspect of the present invention, the signal can be sent using an existing signal line without providing any dedicated signal line.